Pioneering Semiconductor Verification Excellence by Aparna Mohan

Hans India

22-04-2025

With over a decade of experience in pre-silicon verification, Aparna Mohan has emerged as a respected voice in the semiconductor industry. Based in Austin, Texas, she brings a rare combination of academic excellence and deep technical expertise to her work, ensuring the reliability of complex ASIC designs.
'Verification is where my analytical mindset thrives,' Aparna says. 'I've always been driven by the challenge of making sure a design behaves exactly as intended—even under the most unlikely conditions.'
Her academic foundation is as solid as her professional credentials. After earning a Master of Science in Electrical and Computer Engineering from North Carolina State University, she built on her early success as a Third Rank Holder in her undergraduate program at the University of Kerala, India. Her first major role—contributing to satellite systems at the Indian Space Research Organization—sparked her fascination with technological integrity. That fascination soon evolved into a passion for semiconductor design verification.
Aparna's verification expertise spans 14 successful ASIC product tape-outs. She applies a blend of formal and simulation-based methodologies to tackle today's complex verification demands. 'Formal verification allows me to rigorously prove that critical properties always hold, especially in security and control logic,' she explains. 'Meanwhile, simulation with UVM gives us the flexibility to explore vast functional spaces using randomized testing.'
Security verification is one of the most complex challenges in modern semiconductor design. Aparna addresses this through a layered approach. 'Combining formal verification for security protocols with targeted simulation helps us catch both expected and unexpected vulnerabilities,' she says. She also integrates assertion-based and system-level verification techniques, ensuring robust coverage even as design requirements evolve.
A data-driven mindset guides her approach. She closely monitors metrics like coverage, bug detection rates, and cycle efficiency. 'Tracking these indicators tells us where we stand and where we need to focus,' she notes. 'They are the feedback loop that keeps verification on track.'
Her commitment to innovation is equally evident. Aparna has developed reusable verification components, improved debug efficiency, and contributed to multiple technical conferences. 'There's always a better way to solve a problem. Whether it's building smarter environments or adopting new tools, I'm constantly looking to improve how we verify chips.'
Looking ahead, Aparna is optimistic about the role of AI in shaping the future. 'Machine learning will revolutionize how we generate tests, detect bugs, and even suggest strategies,' she predicts. 'As chips get more intelligent, our verification methods must be just as smart.'
Aparna continues to share her insights with the broader verification community, staying actively involved in conferences and forums. 'It's not just about staying current—it's about pushing the field forward together.'