Latest news with #SoCs
United News of India
06-07-2025
- Business
- United News of India
Engineering Progress—Prasad Boraskar's Enduring Legacy in Embedded Systems and Firmware Innovation
In the intricate world of embedded systems and firmware engineering, the bar for technical achievement is set exceptionally high. This domain, which serves as the foundation for advancements in augmented reality, smart security devices, and connected consumer electronics, demands not only advanced academic training but also a rare capacity for innovation and leadership. The professionals who excel here are those whose expertise spans system architecture, design verification, and the automation of complex hardware-software interactions—a profile that is exemplified by Prasad Boraskar. With over 17 years of experience across some of the world's most influential technology companies, Boraskar has built a reputation as a senior embedded systems and firmware engineer whose work consistently drives industry progress. His academic credentials—a Master's degree in Electrical Engineering from the University of Southern California and a Bachelor's degree in Electronics and Telecommunications from Mumbai University—provide a solid foundation for his technical achievements. Throughout his career, Boraskar has focused on the design and verification of firmware for AR devices, security cameras, and embedded platforms, demonstrating a unique ability to bridge theoretical research with practical application. At Meta, Boraskar led verification efforts for AR wearables, developing tools such as the Sensor Synchronization Fixture and the Streaming Data Analyzer. These innovations have reduced manual testing, accelerated product timelines, and set new benchmarks for efficiency and accuracy in the verification of sensor-driven systems. By standardizing timing measurements between sensors and devices, Boraskar's tools have improved data accuracy and enabled teams to deliver higher quality products in less time. The widespread adoption of these methodologies by leading technology firms underscores their originality and significance within the field. Boraskar's impact extends to his work at Apple, where he built an end-to-end firmware update system for Systems on Chip (SoCs), enhancing update reliability and device security for millions of users. His contributions to wireless video transmission and video quality optimization at Netgear have helped improve home security systems that are now widely used in the United States. These achievements reflect a consistent pattern of innovation, where Boraskar's expertise supports robust product development and drives the evolution of the tech industry. The significance of Boraskar's contributions is amplified by the context in which they occur. As embedded systems become increasingly central to the functionality of modern devices, the need for secure, scalable, and efficient solutions grows ever more critical. Boraskar's work in system architecture, firmware design verification, and automation addresses these needs directly, ensuring that products meet the highest standards of reliability and performance. His ability to lead cross-functional teams, manage complex projects, and deliver solutions that align with strategic business objectives further distinguishes him as a leader in his field.
Time of India
07-06-2025
- Business
- Time of India
BEL joins Tata Electronics to develop indigenous electronics, chip solutions
New Delhi: In line with the government's vision for self-reliance, navratna defence PSU Bharat Electronics Limited (BEL) on Friday announced a collaboration with Tata Electronics towards the development of indigenous electronics and semiconductor solutions. The memorandum of understanding (MoU) is a significant step forward for BEL and Tata Electronics in jointly exploring end-to-end solutions to meet domestic requirements., BEL said in a stock exchange filing. BEL and Tata Electronics will explore end-to-end collaboration in areas such as semiconductor fabrication (Fab), Outsourced Semiconductor Assembly and Test (OSAT), and design services. The goal is to meet BEL's present and future needs for advanced components, including Microcontrollers (MCUs), Systems-on-Chip (SoCs), Monolithic Microwave Integrated Circuits (MMICs), and other processors. The MoU was signed by Manoj Jain, Chairman and Managing Director, BEL, and Randhir Thakur, CEO and Managing Director, Tata Electronics, at Bombay House, Tata Group's headquarters in Mumbai. Both companies will also endeavour to develop optimum manufacturing solutions for BEL's products through knowledge sharing, best practices and other resources. Tata Electronics is a prominent global player in the electronics manufacturing industry with fast-emerging capabilities in Electronics Manufacturing Services, Semiconductor Assembly and Test, Semiconductor Foundry, and Design Services. Meanwhile, BEL reported an 18 per cent growth in net profit to Rs 2,127 crore for the January-March quarter of financial year 2024-25 compared with the corresponding figure of Rs 1,797 crore in the same period of the previous year. The company's revenue from operations came in at Rs 9,150 crore, which was a 7 per cent increase over the Rs 8,564 crore reported in the same period of the previous financial year. BEL's board of directors have recommended a final dividend of Rs 0.90 per equity share for the financial year 2024-25. In April, the defence PSU signed a contract with the Indian Air Force valued at Rs 593.22 crore for providing maintenance services for the Akash Missile System to kick off the new financial year 2025-26.
Phone Arena
29-05-2025
- Business
- Phone Arena
Despite EUV ban, Huawei could send 3nm design to SMIC as soon as next year
Exactly one year ago today we told you about Huawei and SMIC's plan to build 3nm chips. A patent filed by Huawei discussed how the latter and the world's third-largest foundry, SMIC, would use self-aligned quadruple patterning (SAQP) lithography to replace the extreme ultraviolet lithography machines that are banned in China. As a result, Huawei would move a step closer to matching the advanced SoCs turned out by TSMC and Samsung Foundry. Fast forward one year to today and a new report out of Taiwan claims that Huawei has started R&D work on a method to produce 3nm chips for the domestic chip industry. Huawei is reportedly pleased with the method used by SMIC to build the 5nm Kirin X90 chip used to power the Mate Book Pro laptop. The foundry supposedly used older Deep Ultraviolet Lithography (DUV) machines, purchased by SMIC before the U.S. chip ban took effect, to make these SoCs. Should Huawei and SMIC continue to rely on DUV machines, the lithography will require the use of multiple impressions on silicon wafers (double, triple, or even quadruple patterning) which pushes up the cost of making a chip especially as yields decline. The use of multiple impressions results in the transfer of circuitry patterns to silicon wafers that are less precise and sharp as such designs would be using the lithography machines that are blocked from getting shipped to China. This lowers the foundry's yield and raises the cost of the chips made using this method. The 5nm Kirin 9000 was made by TSMC in 2020 just before U.S. sanctions hit The 3nm chips made for Huawei will use Gate-All-Around (GAA) transistors which only Samsung Foundry uses at 3nm. GAA transistors surround the channel with the gate on all four sides reducing current leaks and improving the drive current. The result is a more powerful chip with better performance and energy efficiency. Huawei is also supposed to tinker with the usual silicon design and opt for the use of "two-dimensional" materials which is also supposed to improve chip performance and lower energy consumption. Aside from these changes, Huawei is believed to be developing a 3nm node that uses carbon nanotubes instead of silicon transistors. The report calls for Huawei to have completed the design phase for its 3nm node next year, which is also known as the "Tape-out" stage. At that point, Huawei sends the completed and verified design to SMIC allowing the foundry to prepare for the manufacturing of chips using the 3nm node. Huawei was already obtaining 5nm chips from TSMC in 2020 when the U.S. sanctions started to bite preventing Huawei from obtaining cutting-edge chips from foundries like TSMC. Huawei was forced to use 4G Snapdragon application processors made by Qualcomm before the 7nm Kirin 9000s was used to power the Mate 60 Pro. This shocking development brought 5G back to Huawei's handsets.
Associated Press
20-02-2025
- Business
- Associated Press
Advantest Introduces SiConic: Groundbreaking Solution for Automated Silicon Validation
TOKYO, Feb. 20, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic: a scalable solution for automated silicon validation. Designed to address the increasing complexity of advanced systems-on-chip (SoCs), SiConic enables design verification (DV) and silicon validation (SV) engineers to achieve faster sign-off with unparalleled reliability, efficiency and collaboration. Debuting next week at DVCon in San Jose, Calif., SiConic signals Advantest's commitment to transforming the R&D process for its customers. The semiconductor industry is facing unprecedented challenges. Growing SoC design complexity, together with the adoption of 3D packaging and heterogeneous integration, is straining traditional validation workflows. DV and SV teams are under pressure to reduce time-to-market and time-to-quality – even as more devices with more intricate features are being developed within constrictive timelines. Reusing the wealth of verification content developed in pre-silicon would provide an efficiency and quality breakthrough. However, the industry lacks the automated flow and tools to reliably re-use and extend verification tests for silicon validation. SiConic's ecosystem – including EDA partners such as Cadence, Siemens and Synopsys – overcomes this barrier to reuse, enabling engineering efficiency and accelerated test execution on real silicon. SiConic Explorer, the platform's software backbone, offers an automated flow by integrating seamlessly with EDA verification tools based on the Accellera Portable Test and Stimulus Standard (PSS), e.g., the Cadence Perspec System Verifier. In addition, integration with debuggers, such as Lauterbach's TRACE32 debugging tool, accelerates the bring-up of complex multi-IP test cases. SiConic Link is the hardware foundation of the SiConic solution on a bench. With its high-speed I/O (HSIO) capability, SiConic Link supports protocols such as PCIe and USB to enable functional validation with high throughput and rich tracing capabilities during test execution. The test instrument provides control interfaces (e.g., JTAG, SPI) and general-purpose I/Os, improves the debugging workflow and provides extensive control and observability of the device in its target board environment. With SiConic, DV engineers can now leverage familiar pre-silicon techniques, expanding their functional coverage in post-silicon. Similarly, SV engineers benefit from seamless load, set parameters and debug of PSS-based or manually directed content on silicon, thereby enabling rapid and reliable device bring-up and functional characterization. The highly portable solution can be easily scaled for use by distributed global R&D teams collaborating on a complex SoC with diverse IP blocks. SiConic enables confident sign-off decisions through team collaboration and data-driven insights – building trust with customers receiving early samples and expecting reliable ramp and operation during the lifetime of their systems. Industry Support Leading Advantest IC customers and EDA partners are already working with SiConic and seeing the benefits of its performance and productivity advantages. 'With the shift toward increasingly complex multi-chiplet designs, the challenge of pre-silicon verification and post-silicon validation requires new techniques and approaches to ensure quality and performance,' said Alex Starr, AMD Corporate Fellow. 'AMD is delighted that our collaboration on SiConic, particularly focusing on PSS, offers an integrated path to bridge pre- and post-silicon worlds with streamlined, scalable and comprehensive test content.' 'The scaling of AI and mission-critical end applications such as automotive ADAS brings escalating complexity and quality challenges that require new solutions,' said Paul Cunningham, senior vice president and general manager, System Verification Group, Cadence Design Systems. 'Cadence is leading in verification solutions with state-of-the-art, top-level verification by our Perspec System Verifier, based on PSS. We're excited to partner with Advantest to extend our solutions onto silicon – leveraging PSS content to silicon, with the controllability and observability of SiConic, will enable joint customers to reach unprecedented coverage and deep insights into challenging designs.' 'Over decades, our industry has been challenged by test content that requires intense debugging and cross-team collaboration for bring-up on silicon and drawing conclusions in diverse bench and ATE environments. Given today's device complexity and quality demands, we need a breakthrough in efficiency enabled by a systematic and automated flow,' stated Juergen Serrer, chief technology officer and executive vice president, SoC Test Business Unit, Advantest. 'The engineers developing tests in pre-silicon need a unified environment to directly load, debug and gain insights on silicon. SiConic is Advantest's answer to this challenge. We are committed to extending SiConic across all major test types and applications in collaboration with industry-leading customers and partners.' At DVCon, February 24-27 Advantest will present details about SiConic on February 24 at 1:30 p.m. during a tutorial hosted by Cadence. On February 25 at 3:00 p.m., Advantest will present a paper with Qualcomm and Cadence called 'Accelerating Device Sign-off through a Unified Environment for Design Verification, Silicon Validation, and ATE with PSS.' For more information about SiConic and Advantest's full ATE portfolio, you can find it in booth 107 at DVCon. About Advantest Corporation Advantest (TSE: 6857) is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors for applications including 5G communications, the Internet of Things (IoT), autonomous vehicles, high-performance computing (HPC) including artificial intelligence (AI) and machine learning, and more. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also conducts R&D to address emerging testing challenges and applications; develops advanced test-interface solutions for wafer sort and final test; produces scanning electron microscopes essential to photomask manufacturing; and offers system-level test solutions and other test-related accessories. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and an international commitment to sustainable practices and social responsibility. More information is available at . 3061 Zanker Road
