Latest news with #VeriSilicon
Business Upturn
26-06-2025
- Business
- Business Upturn
VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Seriesfor Edge Intelligence
By Business Wire India Published on June 26, 2025, 09:36 IST Shanghai, China: VeriSilicon ( today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices. The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon's multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability. The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications. The ZSP5000 series IPs are backward compatible with VeriSilicon's scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration. 'With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance.' About VeriSilicon VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit: View source version on Disclaimer: The above press release comes to you under an arrangement with Business Wire. Business Upturn takes no editorial responsibility for the same. Ahmedabad Plane Crash Business Wire India, established in 2002, India's premier media distribution company ensures guaranteed media coverage through its network of 30+ cities and top news agencies.
National Post
26-06-2025
- Business
- National Post
VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Series for Edge Intelligence
Article content SHANGHAI — VeriSilicon ( today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices. Article content The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon's multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability. Article content The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications. Article content The ZSP5000 series IPs are backward compatible with VeriSilicon's scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration. Article content 'With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance.' Article content Article content Article content Article content
Business Wire
26-06-2025
- Business
- Business Wire
VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Series for Edge Intelligence
SHANGHAI--(BUSINESS WIRE)--VeriSilicon ( today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices. With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. Share The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon's multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability. The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications. The ZSP5000 series IPs are backward compatible with VeriSilicon's scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration. 'With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications,' said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. 'Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance.' VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit:
Yahoo
26-06-2025
- Business
- Yahoo
VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Series for Edge Intelligence
Highly scalable architecture optimized for computer vision and image workloads with extendable instruction set SHANGHAI, June 26, 2025--(BUSINESS WIRE)--VeriSilicon ( today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices. The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon's multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability. The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications. The ZSP5000 series IPs are backward compatible with VeriSilicon's scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration. "With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications," said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. "Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance." About VeriSilicon VeriSilicon is committed to providing customers with platform-based, all-around, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. For more information, please visit: View source version on Contacts Media Contact: press@ Error in retrieving data Sign in to access your portfolio Error in retrieving data Error in retrieving data Error in retrieving data Error in retrieving data
National Post
12-06-2025
- Business
- National Post
VeriSilicon's AI-ISP Custom Chip Solution Enables Mass Production of Customer's Smartphones
Article content Providing architecture design, software-hardware co-development, and mass production support, and enhancing AI-powered imaging Article content Article content SHANGHAI — VeriSilicon ( recently announced that its AI-ISP custom chip solution has been successfully adopted in a customer's mass-produced smartphones, reaffirming the company's comprehensive one-stop custom silicon service capabilities in AI vision processing. Article content VeriSilicon's AI-ISP custom chip solution can integrate proprietary or third-party Neural Network Processing Unit (NPU) IP and Image Signal Processing (ISP) IP. By combining traditional image processing techniques with AI algorithms, it significantly enhances image and video clarity, dynamic range, and environmental adaptability. The chip solution offers flexible configurations with RISC-V or Arm-based processors, supports MIPI image input/output interfaces, provides LPDDR5/4X memory integration capability, and is compatible with common peripheral interfaces such as UART, I2C, and SDIO. This makes the solution highly adaptable for deployment across various applications including smartphones, surveillance systems, and automotive electronics. Article content For this collaboration, VeriSilicon designed a low-power AI-ISP system-on-chip (SoC) based on the RISC-V architecture, tailored to the customer's specific requirements. It also included a FreeRTOS real-time Software Development Kit (SDK). The customized SoC was fully optimized for seamless interoperability with the customer's main processor platform and has since been successfully deployed in multiple smart devices, achieving large-scale production. This success highlights VeriSilicon's robust capabilities in heterogeneous computing, software-hardware co-optimization, and system-level integration and verification. Article content 'AI-powered imaging has become a key differentiator in the competitive smartphone market, driving increasing demand for high-performance and low-power image processing solutions,' said Wiseway Wang, Executive Vice President and General Manager of the Custom Silicon Platform Division at VeriSilicon. 'With full-spectrum capabilities ranging from IP licensing and chip architecture design to system-level software and hardware development, tape-out, packaging and testing, as well as mass production, VeriSilicon offers end-to-end custom silicon services leveraging its extensive design service experience and proven mass production capabilities. The successful mass production of this customer's chip further validates our strength in high-end silicon design services. Moving forward, we will continue to innovate and improve our offerings, empowering customers to accelerate the launch of differentiated products with efficient, high-quality custom chip solutions.' Article content Article content
